Integrated circuits with combined control and driver functions are often referred to as smart power devices. Smart power devices combine high intelligence with low power dissipation. They typically have power Metal Oxide Semiconductor, MOS, Field Effect Transistors, FETs, in their output stages designed to operate at higher voltages, such as 15-80 volts as opposed to the normal Complementary Metal Oxide Semiconductor, CMOS, logic voltage of typically 5 volts or less, and logic devices incorporated on the same integrated circuit so that both a driver function and a controller function are provided in a single chip. Many applications exist for smart power devices such as Liquid Crystal Display, LCD, displays, electro/mechanical devices, automobile electronic devices, projection TV, and even High Definition, HDTV.
A technique for fabricating high voltage, HV, MOS devices is described in an article entitled "High Voltage Thin Layer Devices (RESURF Devices)," IEDM Proceedings, 1979, pp 238-241. This technique uses a shallow lightly doped region between the drain and channel regions of the device. This shallow lightly doped region is referred to as a drift region because of the low amount of current carriers (carriers being electrons or "holes") that are available due to the low level of impurity doping and the device is known as a Reduced Surface Field, RESURF, device.
RESURF techniques are utilized in manufacturing high voltage N-channel Lateral Double Diffused MOS, HV NMOS, devices and high voltage P-channel Lateral Double Diffused MOS, HV PMOS, devices. However, problems exist in designing and manufacturing smart power devices containing such RESURF high voltage devices. Typically the drain to source on-resistance of an HV PMOS device is relatively high. For example, an HV PMOS device described in an article entitled "A Coplanar CMOS Power Switch," IEEE J. Solid-State Circuits, vol. SC-16, pp 212-226, June 1981, uses a lightly doped pinched resistance as the drift region. Similarly, the drain to source on-resistance of an HV NMOS device is dependant on the length of the semiconductive drift region.
FIG. 1 shows a cross-sectional view of an integrated circuit containing a high voltage NMOS device 6 and a high voltage PMOS device 7 made in a conventional manner. HV NMOS device 6 has a drift region 21 between a drain 22 and a channel region 29. A gate field oxide 23 overlies a substantial portion of drift region 21 adjacent to drain 22. When device 6 is turned on, current flowing from drain 22 to channel region 29 passes through drift region 21 and encounters a resistance due to the bulk resistance of the lightly doped n-type material in drift region 21. The amount of this bulk resistance is proportional to a length d4 of drift region 21. Length d4 is dependant on a length d3 of field oxide 23, since drift region 21 must extend past the edge of field oxide 23 where drift region 21 comes in contact with channel region 29. The bulk resistance of drift region 21 may be a significant percentage of the total drain to source on-resistance, R.sub.ds(on), of device 6.
Still referring to FIG. 1, HV PMOS device 7 similarly has a drift region 41 between a drain 42 and a channel region 49. A gate field oxide 43 overlies a substantial portion of drift region 41 adjacent to drain 42. When device 7 is turned on, current flowing from channel region 49 to drain 42 passes through drift region 41 and encounters a resistance due to the bulk resistance of the lightly doped p-type material in drift region 41. The amount of this bulk resistance is proportional to a length d2 of drift region 41. Length d2 is dependant on a length d1 of a field oxide 43, since drift region 41 must extend past the edge of field oxide 43 where the drift region 41 comes in contact with channel region 49. The bulk resistance of drift region 41 may be a significant percentage of the total drain to source on-resistance, R.sub.ds(on), of device 7.
It is accordingly an object of the invention to provide a simple method to manufacture smart power devices which contain high voltage PMOS and high voltage NMOS devices that have lower on-resistance.
Other objects and advantages will be apparent to those of ordinary skill in the art having reference to the following figures and specification.